THS7347_15 Datasheet, PDF (9/33 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
www.ti.com
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
TIMING REQUIREMENTS FOR I²C INTERFACE⁽¹⁾⁽²⁾
At V_DD = 2.7 V to 5 V.
STANDARD MODE
FAST MODE
PARAMETER
MIN
MAX
MIN
MAX
f_SCL
t_w(H)
t_w(L)
t_r
t_f
t_su(1)
t_h(1)
t_(buf)
t_su(2)
t_h(2)
t_su(3)
C_b
Clock frequency, SCL
Pulse duration, SCL high
Pulse duration, SCL low
Rise time, SCL and SDA
Fall time, SCL and SDA
Setup time, SDA to SCL
Hold time, SCL to SDA
Bus free time between stop and start conditions
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
Capacitive load for each bus line
0
100
0
400
4
0.6
4.7
1.3
1000
300
300
300
250
100
0
0
4.7
1.3
4.7
0.6
4
0.6
4
0.6
400
400
(1) The THS7347 I²C address = 01011(A1)(A0)(R/W). See the Applications Information section for more information.
(2) The THS7347 was designed to comply with version 2.1 of the I²C specification.
UNIT
kHz
μs
μs
ns
ns
ns
ns
μs
μs
μs
μs
pF
SCL
t _w(H)
t _w(L)
t_r
t_f
t _su(1)
t _h(1)
SDA
Figure 1. SCL and SDA Timing
SCL
SDA
t _su(2)
t _h(2)
t _su(3)
t _(buf)
Start Condition
Stop Condition
Figure 2. Start and Stop Conditions
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