THS7347_15 Datasheet, PDF (24/33 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
THS7347 Read Phase 2:
Step 7
0
I²C Start (Master)
S
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Step 8
I²C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
1
Where each X Logic state is defined by I²C-A1 and I²C-A0 pins being tied to either V_DD or GND.
Step 9
9
I²C Acknowledge (Slave)
A
Step 10
I²C Read Data (Slave)
7
Data
6
Data
5
Data
4
Data
3
Data
2
Data
1
Data
0
Data
Where Data is determined by the logic values contained in the Channel Register.
Step 11
9
I²C Not-Acknowledge (Master)
A
Step 12
0
I²C Stop (Master)
P
24
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