THS7347_15 Datasheet, PDF (20/33 Pages) Texas Instruments – 3-Channel RGBHV Video Buffer with I2C Control, 2:1 Input Mux, Monitor Pass-Through, and Selectable Input Bias Modes

THS7347
SLOS531B – MAY 2007 – REVISED OCTOBER 2011
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Channel Register Bit Descriptions
Each bit of the subaddress (channel selection) control register as described in the previous section allows the
user to individually control the THS7347 functionality. This process allows the user to control the functionality of
each channel independently with regard to the other channels. The bit description for Channel 1 through Channel
3 is shown in Table 3, while the H/V sync channels and the analog channel states are described in Table 4.
Table 3. THS7347 Channel Register (Channel 1 through Channel 3) Bit Decoder Table.
Use with Register Bit Codes (0000 0001), (0000 0010), and (0000 0011)
BIT
(MSB)
7
6, 5, 4, 3
2, 1, 0
(LSB)
FUNCTION
Sync-Tip Clamp Filter
MUX Selection
Input Mode
+
Operation
BIT VALUE(S)
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
000
001
010
011
100
101
110
111
RESULT
500-kHz filter on the STC circuit
5-MHz filter on the STC circuit
MUX Input A
MUX Input A
MUX Input A
MUX Input A
MUX Input A
MUX Input B
MUX Input B
MUX Input B
MUX Input B
MUX Input B
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Reserved; do not care
Disables both monitor and buffer paths of the respective
channel/register
Channel Mute
Input Mode = dc
Input Mode = dc + Shift
Input Mode = ac-bias
Input Mode = ac-STC with low bias
Input Mode = ac-STC with mid bias
Input Mode = ac-STC with high bias
Bit 7 (MSB): Controls the sync-tip clamp filter. Useful only when AC-STC input mode is selected.
Bits 6, 5, 4, 3: Selects the Input MUX channel.
Bits 2, 1, and 0 (LSB): Configures the channel mode and operation. See Table 4, Bits 6 and 5, for more
information with respect to the enable/disable state.
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