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OPA316_16 Datasheet, PDF (9/48 Pages) Texas Instruments – 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier
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OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
Electrical Characteristics (continued)
VS (total supply voltage) = (V+) – (V–) = 1.8 V to 5.5 V.
At TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER
TEST CONDITIONS
MIN
TYP
OUTPUT
VS = 1.8 V, RL = 10 kΩ, TA= –40°C to 125°C
VO
Voltage output swing from supply VS = 5.5 V, RL = 10 kΩ, TA= –40°C to 125°C
rails
VS = 1.8 V, RL = 2 kΩ, TA= –40°C to 125°C
VS = 5.5 V, RL = 2 kΩ, TA= –40°C to 125°C
ISC
Short-circuit current
VS = 5 V
±50
ZO
Open-loop output impedance
VS = 5 V, f = 10 MHz
250
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current per amplifier
Power-on time
SHUTDOWN (VS = 1.8 V to 5.5 V)(2)
IQSD
Quiescent current, per device
VS = 5 V, IO = 0 mA, TA= –40°C to +125°C
VS = 0 V to 5.5 V
All amplifiers disabled, SHDN = VS–
One amplifier disabled (OPA2316S)
1.8
400
200
0.01
345
VIH
High voltage (enabled)
VIL
Low voltage (disabled)
tON
Amplifier enable time(3)
tOFF
Amplifier disable time(3)
SHDN pin input bias current (per
pin)
TEMPERATURE
Amplifier enabled
Amplifier disabled
Full shutdown, G = 1, VOUT = 0.9 × VS / 2(4)
Partial shutdown, G = 1, VOUT = 0.9 × VS / 2(4)
G = 1, VOUT = 0.1 × VS / 2
VIH = 5 V
VIL = 0 V
(V+) – 0.5
13
10
5
3.5
2.5
Specified temperature
–40
TA
Operating temperature
–55
Tstg
Storage temperature
–65
MAX
15
30
60
120
5.5
500
1
(V–) + 0.2
125
150
150
UNIT
mV
mV
mV
mV
mA
Ω
V
µA
µs
µA
µA
V
V
µs
µs
µs
pA
pA
°C
°C
°C
(2) Ensured by design and characterization; not production tested.
(3) Enable time (tON) and disable time (tOFF) are defined as the time interval between the 50% point of the signal applied to the SHDN pin
and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(4) Full shutdown refers to the dual OPA2316S having both channels A and B disabled (SHDN_A = SHDN_B = VS–). For partial shutdown,
only one SHDN pin is exercised; in partial mode, the internal biasing and oscillator remain operational and the enable time is shorter.
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