OPA316_16 Datasheet, PDF (6/48 Pages) Texas Instruments – 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier

OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
www.ti.com
Thermal Information: OPA316 (continued)
R_θJC(bot)
THERMAL METRIC⁽¹⁾
Junction-to-case(bottom) thermal resistance⁽⁷⁾
SOT23 (DBV)
5 PINS
N/A
OPA316
SC70 (DCK)
5 PINS
N/A
UNIT
°C/W
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.5 Thermal Information: OPA2316
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case(bottom) thermal resistance⁽⁷⁾
SO (D)
8 PINS
127.2
71.6
68.2
22
67.6
N/A
OPA2316
MSOP (DGK)
8 PINS
186.6
78.8
107.9
15.5
106.3
N/A
DFN (DRG)
8 PINS
56.3
72.2
31
2.3
21.2
10.9
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6.6 Thermal Information: OPA2316S
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case(bottom) thermal resistance⁽⁷⁾
MSOP (DGS)
10 PINS
189.6
73.9
110.7
13.4
109.1
N/A
OPA2316S
RUG (QFN)
10 PINS
158
52
88
1
87
N/A
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
6
Submit Documentation Feedback
Copyright © 2014–2016, Texas Instruments Incorporated
Product Folder Links: OPA316 OPA2316 OPA2316S OPA4316