OPA316_16 Datasheet, PDF (5/48 Pages) Texas Instruments – 10-MHz, Low-Power, Low-Noise, RRIO, 1.8-V CMOS Operational Amplifier

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OPA316, OPA2316, OPA2316S, OPA4316
SBOS703E – APRIL 2014 – REVISED JUNE 2016
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted)⁽¹⁾
Supply voltage
Voltage ⁽²⁾
Signal input pins
Current ⁽²⁾
Output short-circuit⁽³⁾
Common-mode
Differential
T_A
Operating temperature
T_J
Junction temperature
T_stg
Storage temperature
MIN
(V–) – 0.5
–10
–55
–65
MAX
7
(V+) + 0.5
(V+) – (V–) + 0.2
10
Continuous
150
150
150
UNIT
V
V
V
mA
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5 V beyond the supply
rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
over operating free-air temperature range (unless otherwise noted)
V_(ESD)
Electrostatic ^{Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)}
discharge
Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
±4000
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_S Supply voltage
Specified temperature
MIN
MAX UNIT
1.8
5.5 V
–40
125 °C
6.4 Thermal Information: OPA316
THERMAL METRIC⁽¹⁾
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case(top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
SOT23 (DBV)
5 PINS
221.7
144.7
49.7
26.1
49
OPA316
SC70 (DCK)
5 PINS
263.3
75.5
51
1
50.3
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
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