DS99R105_13 Datasheet, PDF (9/29 Pages) Texas Instruments – DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
PWDWN
2.0V
TCLK
DOUT±
t_PLD
TRI-STATE
t_ZHD or
t_ZLD
Output
Active
0.8V
t_HZD or
t_LZD
TRI-STATE
Figure 8. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays
DIN
SYMBOL N
SYMBOL N+1
SYMBOL N+2
SYMBOL N+3
t_SD
TCLK
DOUT0-23
DCA, DCB
STOP START
STOP START
STOP START
STOP START
STOP
SYMBOL N-4 ^{BIT BIT} SYMBOL N-3 ^{BIT BIT} SYMBOL N-2 ^{BIT BIT} SYMBOL N-1 ^{BIT BIT} SYMBOL N ^BIT
012
23
012
23
012
23
012
23
012
23
See Serializer Timing Requirements for TCLK Note (1).
Figure 9. Serializer Delay
Ideal Data Bit
Beginning
Ideal Data Bit
End
TxOUT_E_O
t_BIT(1/2UI)
t_BIT(1/2UI)
Ideal Center Position (t_BIT/2)
t_BIT (1UI)
Figure 10. Transmitter Output Eye Opening (TxOUT_E_O)
24
DIN
DOUT+
R_L
DOUT-
TCLK
VOD = (D_OUT+) – (D_{OUT -})
Differential output signal is shown as (D_OUT+) – (D_{OUT -}), device in Data Transfer mode.
Figure 11. Serializer VOD Diagram
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