DS99R105_13 Datasheet, PDF (17/29 Pages) Texas Instruments – DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R105, DS99R106
www.ti.com
SNLS242D – MARCH 2007 – REVISED APRIL 2013
Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times
the TCLK frequency. For example, if TCLK is , the serial rate is 40 x 28 = 1.12 Giga bits per second. Since only
24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 40
MHz, the payload data rate is 40 x 24 = 960 Mbps. TCLK is provided by the data source and must be in the
range of 3 MHz to 40 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection as
shown in Figure 20. The outputs transmit data when the enable pin (DEN) is high and TPWDNB is high. The
DEN pin may be used to TRI-STATE the outputs when driven low.
When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and
synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded
clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin.
The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high,
data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the
RRFB input. ROUT(0-23), LOCK and RCLK outputs will each drive a maximum of 8 pF load with a 40 MHz clock.
REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer.
RESYNCHRONIZATION
If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock
edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer
then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock
edge, identifies it and then proceeds through the locking process.
The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid.
The system must monitor the LOCK pin to determine whether data on the ROUT is valid.
POWERDOWN
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down
mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is
driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing
supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must
lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before
data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown
mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the powerdown
state, the system drives RPWDNB high.
Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer
will initialize and assert LOCK high when it is locked to the encoded clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both
driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state
as long as all other control pins remain static (TPWDNB, TRFB).
When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver
output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the
state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and
power-off (V_DD = 0V).
PRE-EMPHASIS
The DS99R105 features a Pre-Emphasis mode used to compensate for long or lossy transmission media. Cable
drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during
transitions to counteract cable loading effects. The transmission distance will be limited by the loss
characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce
the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster
transitions, increased eye openings, and improved signal integrity. The ability of the DS99R105 to use the Pre-
Emphasis feature will extend the transmission distance in most cases.
Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS99R105 DS99R106
Submit Documentation Feedback
17