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| DS99R105_13 Datasheet, PDF (8/29 Pages) Texas Instruments – DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer | |||
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DS99R105, DS99R106
SNLS242D â MARCH 2007 â REVISED APRIL 2013
tTCP
TCLK
VDD/2
VDD/2
VDD/2
tDIS
tDIH
DIN [0:23] VDD/2
Setup
See Serializer Timing Requirements for TCLK Note (2).
Hold
VDD/2
VDD
0V
Figure 6. Serializer Setup/Hold Times
Parasitic package and
Trace capcitance
DEN VCC/2
(single-ended)
0V
DOUT±
(differential)
200 mV
DEN VCC/2
(single-ended)
0V
200 mV
DOUT±
(differential)
DEN
DOUT+
DOUT-
5 pF
100:
CLK1
tLZD
VCC/2
CLK1
tTCP
tTCP
tZLD
tZHD
DCA
DCA DCA DCA
$OO GDWD ³0´V
DCA DCA DCA DCA
tHZD
VCC/2
DCA DCA DCA DCA
$OO GDWD ³1´V
DCA DCA DCA DCA
CLK0
tTCP
tTCP
CLK0
Figure 7. Serializer TRI-STATE Test Circuit and Delay
www.ti.com
0V
200 mV
0V
200 mV
8
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Product Folder Links: DS99R105 DS99R106
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