DS99R105_13 Datasheet, PDF (21/29 Pages) Texas Instruments – DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
3.3V
C5
C1
C6
C2
DS99R106 (DES)
VDDIR
VDDPR0
VDDPR1
VDDOR1
VDDOR2
VDDOR3
VDDR0
VDDR1
Serial
LVDS
Interface
C9
C10
3.3V
GPO if used, or tie High (ON)
RIN+
RIN-
REN
RRFB
RPWDNB
Notes:
RPWDNB = System GPO
REN = High (ON)
RRFB = High (Rising edge)
RESRVD = Low
RESRVD
VSSPR0
VSSPR1
VSSR0
VSSR1
VSSIR
VSSOR1
VSSOR2
VSSOR3
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
ROUT10
ROUT11
ROUT12
ROUT13
ROUT14
ROUT15
ROUT16
ROUT17
ROUT18
ROUT19
ROUT20
ROUT21
ROUT22
ROUT23
RCLK
LOCK
3.3V
C3
C7
C4
C8
LVCMOS
Parallel
Interface
C1 to C4 = 0.01 P F
C5 to C8 = 0.1 P F
C9, C10 = 100 nF; 50WVDC, NPO or X7R
TPWDNB
(Pin 9)
L
H
H
H
RPWDNB
(Pin 1)
L
H
H
H
Figure 22. DS99R106 Typical Application Connection
TRUTH TABLES
DS99R105 Serializer Truth Table
DEN
(Pin 18)
Tx PLL Status
(Internal)
LVDS Outputs
(Pins 19 and 20)
X
X
Hi Z
L
X
Hi Z
H
Not Locked
Hi Z
H
Locked
Serialized Data with Embedded Clock
DS99R106 Deserializer Truth Table
REN
(Pin 48)
Rx PLL Status
(Internal)
ROUTn and RCLK
(See DS99R105 Pin
Diagram)
LOCK
(Pin 17)
X
X
Hi Z
Hi Z
L
X
Hi Z
L = PLL Unocked;
H = PLL Locked
H
Not Locked
Hi Z
L
H
Locked
Data and RCLK Active
H
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