DS99R105_13 Datasheet, PDF (7/29 Pages) Texas Instruments – DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

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DS99R105, DS99R106
SNLS242D – MARCH 2007 – REVISED APRIL 2013
AC Timing Diagrams and Test Circuits
Device Pin Name
Signal Pattern
TCLK
ODD DIN
EVEN DIN
See Serializer Timing Requirements for TCLK Note (1).
Figure 2. Serializer Input Checker-board Pattern
Device Pin Name
Signal Pattern
RCLK
ODD ROUT
EVEN ROUT
See Serializer Timing Requirements for TCLK Note (1).
Figure 3. Deserializer Output Checker-board Pattern
DOUT+
10 pF
DOUT-
100:
Differential
80%
Signal _20%
10 pF
Vdiff = (DOUT+) - (DOUT-)
t_LLHT
80%
Vdiff = 0V
20%
t_LHLT
Figure 4. Serializer LVDS Output Load and Transition Times
TCLK
80%
20%
80%
20%
V_DD
0V
t_CLKT
t_CLK
Figure 5. Serializer Input Clock Transition Times
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