DRV8808 Datasheet, PDF (9/38 Pages) Texas Instruments – COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER

DRV8808
www.ti.com
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
ELECTRICAL CHARACTERISTICS (continued)
T_J = 0°C to 135°C, V_M = 7 V to 38 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
nORT Delay: Startup Sequence ^{(16) (17)}
Tord1
nORT delay 1
Reset deassertion from Vth_VM+ < V_M, for
DC/DC wake up failing
Tord3
dc-dc turn on delay
From one dc-dc wake up to following dc-dc to
go soft-start sequence
Tord4
nORT delay 4
nReset Input⁽¹⁶⁾
Reset deassertion from 2nd dc-dc wake up
Treset
nReset assertion to nORT
assertion delay
nReset falling to nORT failing
H-Bridge Drivers (OUTX+ and OUTX–) Condition: V_M = 15 V to 38 V ⁽¹⁸⁾
I_OUT1(max)
Peak output current 1
Less than 500-ns period
I_OUT2(max)
Peak output current 2
Less than 100-ms period
R_DSON
FET ON resistance at 0.8 A
T_J = 70°C
T_J = 135°C
I_CEX
Output leakage current
VOUTX = 0 V or 10
I_{OC Motor}
Motor overcurrent threshold for
each H-bridge ⁽¹⁸⁾
Fchop
Motor chopping frequency =
FOSCM/8
DC Motor Drivers
t_r
Rise time
V_M = 35 V
20% to 80%
t_f
Fall time
V_M = 35 V
20% to 80%
t_PDOFF
Enable or strobe detection
to sink or source gate OFF delay
t_COD
Crossover delay time to prevent
shoot through
t_PDON
t_Ideg
T_blank
Enable or strobe detection
to sink or source gate ON delay
MISD BLANK
TBLANK
[00] ⁽²⁰⁾
[01] ⁽²¹⁾
[10] ⁽²²⁾
[11] ⁽²³⁾
[00] ⁽²⁴⁾
[01] ⁽²⁵⁾
[10] ⁽²⁶⁾
[11] ⁽²⁷⁾
MIN
200
5
60
3
90
50
50
50
100 ⁽¹⁹⁾
1.80
1.20
2.35
2.95
3.05
1.90
4.15
5.30
TYP MAX UNIT
300
390
ms
10
15 ms
120
180
ms
5
10
μs
6.8
A
2.42
A
0.55 0.65
Ω
0.7 0.85
10 μA
8
A
100
110 kHz
200
nS
200
nS
150
400
nS
600 1000
nS
750
nS
2.25 2.95
μs
1.50 2.30
3.00 3.65
3.75 4.30
3.45 5.50
μs
2.20 4.15
4.70 6.75
5.95 8.25
(16) This includes asynchronous timing deviation between the event to the timer clock.
(17) nORT assertion delay is configurable and defined in the serial register section.
(18) When the overcurrent is detected, all the H-bridges are shut down and assert nORT per shutdown configuration.
(19) t_COD, P_minp, and P_mine not production tested.
(20) 3 to 4 periods Fosc/4 + 1 Fosc
(21) 2 to 3 periods Fosc/4 + 1 Fosc
(22) 4 to 5 periods Fosc/4 + 1 Fosc
(23) 5 to 6 periods Fosc/4 + 1 Fosc
(24) 3 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(25) 2 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(26) 4 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
(27) 5 Fosc/8 (can add up to 1 additional Fosc/8 + 1.5 Fosc at phase or enable change due to asynchronous ambiguity)
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