DRV8808 Datasheet, PDF (15/38 Pages) Texas Instruments – COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER

DRV8808
www.ti.com
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
Operation Setup Register Bit Assignment
Table 2. Setup Registers ^{(1) (2) (3)}
BANK
BIT
0
1
2
3
4
5
6
7
0
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
1
9
10
11
12
13
14
15
FUNCTION
Tblank A 0
Tblank A 1
Tblank B 0
Tblank B 1
Tblank C 0
Tblank C 1
DC-DC A Minoff Time
DC-DC A SW
DC-DC B SW
DC-DC C SW
MOTOR CHOPPING 0
MOTOR CHOPPING 1
RESET DELAY CONTROL
LDO ENABLE
DC-DC B Minoff Time
Bank Change
MISD BLANK AB 0
MISD BLANK AB 1
MISD BLANK C 0
MISD BLANK C 1
VRS A
VRS A Level 0
VRS A Level 1
DC-DC C Minoff Time
VRS B
VRS B Level 0
VRS B Level 1
DEEP SLEEP
VRS C
VRS C Level 0
VRS C Level 1
Bank Change
DEFAULT
0
0
0
0
0
0
0
1
CSELECT
CSELECT
0
0
0
Note 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COMMENT
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
00: 3.75 μs, 01: 2.50 μs
10: 5.00 μs, 11: 6.25 μs
0: 2.2 μs, 1: 6.6 μs
0: On
1: Off
00: 100 kHz, 01: 50 kHz
10: 133 kHz, 11: 200 kHz
0: Disable, 1: Enable
0: On, 1: Off
0: 2.2 μs, 1: 6.6 μs
0: Bank0, 1: Bank1
00: 2.25 μs, 01: 1.50 μs
10: 3.00 μs, 11: 3.75 μs
00: 2.25 μs, 01: 1.50 μs
10: 3.00 μs, 11: 3.75 μs
0: Disable, 1: Enable
VRSA = 0:
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSA = 1:
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
0: 2.2 μs, 1: 6.6 μs
0: Disable, 1: Enable
VRSB = 0:
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSB = 1:
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
0: Disable, 1: Enable
0: Disable, 1: Enable
VRSC = 0:
00: 1.4 A, 01: 1.7 A
10: 1.9 A, 11: 2.2 A
VRSC = 1:
00: 185 mV, 01: 210 mV
10: 260 mV, 11: 310 mV
0: Bank0, 1: Bank1
(1) The LDO default follows the DC/DC B default value based on CSELECT.
(2) All bits go to default for VM < Vth_VM, nReset = L.
(3) RESET DELAY CONTROL set to 1 delays nORT assertion by 100 us typical. Range is 85 us to 125 us.
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