DRV8808 Datasheet, PDF (32/38 Pages) Texas Instruments – COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER

DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
www.ti.com
Blanking Time Insertion Timing for DC Motor Driving
For the dc motor-driving H-bridge, tBlank is inserted at each phase reversal and following each chopping cycle
(once in every eight OSCM clocks).
For a large n number (5 or 6), tBlank setup may decrease the Itrip detect window. Care must be taken when
optimizing this in the system.
Case A: Phase duty = 25%
• A*1 for setup bit = (1,0)
• A*2 for setup bit = (0,1)
OSCM
Phase
fChop
tBlank (0,1)
(see Note A)
Resync
2.5 µs
Resync
8 ´ OSCM Clocks
2.5 µs
2.5 µs
Resync
2.5 µs
tBlank (1,0)
(see Note B)
5 µs
5 µs
5 µs
A. Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B. Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
Case B: Phase duty = 40%
• B*1 for setup bit = (1,0)
• B*2 for setup bit = (0,1)
<5 µs
OSCM
Resync
2.5 µs
5 µs
Phase
fChop
tBlank (0,1)
(see Note A)
Resync
8 ´ OSCM Clocks
2.5 µs
Resync
8 ´ OSCM Clocks
2.5 µs
Resync
<2.5 µs ^{2.5 µs}
tBlank (1,0)
(see Note B)
5 µs
5 µs
<5 µs
5 µs
A. Setup register bit <1:0> = (1,0), tBlank = 5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
B. Setup register bit <1:0> = (0,1), tBlank = 2.5 μs (or bits <3:2>/<5:4> for H-bridge B/C channel)
Resync
2.5 µs
5 µs
32
Copyright © 2009–2011, Texas Instruments Incorporated