DRV8808 Datasheet, PDF (14/38 Pages) Texas Instruments – COMBINATION MOTOR DRIVER WITH DC-DC CONVERTER

DRV8808
SLVS857A – DECEMBER 2009 – REVISED AUGUST 2011
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VM
nPUC
(internal)
nORT
nSLEEP_ext
nSLEEP_int is forced HI until nORT is HI.
Once nORT is HI, nSLEEP_int follows nSLEEP_ext.
nSLEEP_int
[internal only]
STB (or) ENA
STB (or) ENA going high when nSLEEP_int is LO causes
data transfer from shift registers to set up registers
??? Valid Data
Undefined
???
Valid Data
Set Up regs
???
Valid Data
Shift Regs
Shift Register data is valid and defined only
after a serial command
A. During startup (VM rising), internally nSLEEP de-asserted to HI, suppressing false data latching caused by a rising
edge on the STB signal. nSLEEP will remain HI until nORT is released (120 ms after dc-dc regulators come up).
Figure 5. Serial Peripheral Interface STROBE Blocking During Power Up
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