DRV110_15 Datasheet, PDF (9/24 Pages) Texas Instruments – Power-Saving Solenoid Controller

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Feature Description (continued)
DRV110
SLVSBA8B – MARCH 2012 – REVISED JULY 2015
Figure 3. PEAK and HOLD Mode V_REF Settings
Frequency of the internal PWM clock signal, PWM_CLK, that triggers each OUT pin ON-cycle can be adjusted by
external resistor, R_OSC, connected between OSC and GND. Frequency as a function of resistor value is shown in
Figure 4. Default frequency is used when OSC is connected to GND directly. PWM frequency as a function of
external fixed adjustment resistor value (greater than 66.67 kΩ) is given below.
60kHz
f_PWM = _ROSC × 66.67kW;66.67kW < R_OSC < 2MW
(4)
Figure 4. PWM Clock Frequency Setting
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