DRV110_15 Datasheet, PDF (4/24 Pages) Texas Instruments – Power-Saving Solenoid Controller

DRV110
SLVSBA8B – MARCH 2012 – REVISED JULY 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings⁽¹⁾⁽²⁾
VIN Input voltage
Voltage on EN, STATUS, PEAK, HOLD, OSC, SENSE, KEEP
Voltage on OUT
T_J Operating virtual junction temperature
T_stg Storage temperature
MIN
MAX
UNIT
–0.3
20
V
–0.3
7
V
–0.3
20
V
–40
125
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged device model (CDM), per JEDEC specification JESD22-
C101 ⁽²⁾
VALUE
±2000
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
I_Q
Supply current
V_IN
Device will start sinking current when V_IN > 15 V to limit V_IN
C_IN
Input capacitor between VIN and GND ⁽¹⁾
L
Solenoid inductance
1
1.5
6
15
1
4.7
1
T_A
Operating ambient temperature
–40
(1) 4.7-µF input capacitor and full wave rectified 230-Vrms AC supply results in approximately 500-mV supply ripple.
MAX
3
105
UNIT
mA
V
µF
H
°C
6.4 Thermal Information
DRV110
THERMAL METRIC
PW [TSSOP]
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
Junction-to-top characterization parameter⁽⁴⁾
Junction-to-board characterization parameter⁽⁵⁾
Junction-to-case (bottom) thermal resistance⁽⁶⁾
8 PINS
183.8
69.2
112.6
10.4
110.9
N/A
14 PINS
122.6
51.2
64.3
6.5
63.7
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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