BQ4013_14 Datasheet, PDF (9/15 Pages) Texas Instruments – 128 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

Not Recommended For New Designs
bq4013/Y/LY
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SLUS121A – MAY 1999 – REVISED MAY 2007
Table 3. WRITE CYCLE (T_A = T_OPR, V_CC(min)≤ V_CC≤ V_CC(max))
PARAMETER
TEST CONDITIONS
-70
MIN MAX
-85
MIN MAX
-120
MIN MAX
UNIT
t_WC Write cycle time
t_CW Chip enable to end of write
t_AW Address valid to end of write
t_AS
Address setup time
70
See ⁽¹⁾
65
See ⁽¹⁾
65
Measured from address valid to beginning
of write.⁽²⁾
0
85
120
75
100
75
100
0
0
t_WP Write pulse width
Measured from beginning of write to end of
write. ⁽¹⁾
55
65
85
t_WR1 Write recovery time (write cycle 1)
Measured from WE going high to end of
write cycle.⁽³⁾
5
5
5
t_WR2 Write recovery time (write cycle 2)
Measured from CE going high to end of
write cycle.⁽³⁾
15
15
ns
15
t_DW Data valid to end of write
Measured to first low-to- high transition of
either CE or WE.
30
35
45
t_DH1 Data hold time (write cycle 1)
Measured from WE going high to end of
write cycle.⁽⁴⁾
0
0
0
t_DH2 Data hold time (write cycle 2)
Measured from CE going high to end of
write cycle.⁽⁴⁾
0
0
0
t_WZ Write enbled to output in high Z
t_OW Output active from end of write
I/O pins are in output state.⁽⁵⁾
I/O pins are in output state. ⁽⁵⁾
0 25
5
0
30
0 40
5
5
(1) A write ends at the earlier transition of CE going high and WE going high.
(2) A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition of CE going low and WE going low.
(3) Either t_WR1 or t_WR2 must be met.
(4) Either t_DH1 or t_DH2 must be met.
(5) If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in high-impedance state.
t_WC
Address
t_AW
t_WR1
t_CW
CE
t_AS
t_WP
WE
t_DW
t_DH1
D_IN
Data−In Valid
t_WZ
t_OW
D_OUT
Data Undefined (1)
High−Z
(1) CE or WE must be high during address transition.
(2) Because I/O may be active (OE low) during this period, data input signals of opposite polarity to the outputs must not
be applied.
(3) If OE is high, the I/O pins remain in a state of high impedance.
Figure 8. Write Cycle No. 1 (WE-Controlled) ^(1)(2)(3)
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