BQ4013_14 Datasheet, PDF (12/15 Pages) Texas Instruments – 128 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

bq4013/Y/LY
Not Recommended For New Designs
SLUS121A – MAY 1999 – REVISED MAY 2007
www.ti.com
Table 5. 3.3-V POWER-DOWN/POWER-UP (T_A = T_OPR)
PARAMETER
TEST CONDITIONS
MIN TYP⁽¹⁾ MAX UNIT
t_F
V_CC slew, 3 V to 0 V
300
t_R
V_CC slew, V_SO to V_{PFD (max)}
100
t_CER
Chip enable recovery time
Time during which SRAM is write-protected after
V_CC passes V_PFD on power-up.
10
t_DR
Data-retention time in absence of V_CC T_A = 25°C⁽²⁾
10
µs
85 ms
years
(1) Typical values indicate operation at T_A = 25°C, V_CC = 3.3 V.
(2) Batteries are disconnected from circuit until after V_CC is applied for the first time. Data retention time (t_DR) is the accumulated time in
absence of power beginning when power is first applied to the device.
V_CC
3.0 V
V_PFD
V_PFD(max)
V_SO
V_SO
t_DR
t_F
t_R
t_CER
CE
Figure 11. 3.3-V Power-Down/Power-Up Timing
CAUTION:
Negative undershoots below the absolute maximum rating of -0.3 V in
battery-backup mode may affect data integrity.
12
Submit Documentation Feedback