BQ4013_14 Datasheet, PDF (7/15 Pages) Texas Instruments – 128 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

Not Recommended For New Designs
bq4013/Y/LY
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SLUS121A – MAY 1999 – REVISED MAY 2007
Table 2. READ CYCLE (T_A = T_OPR, V_CC(min)≤ V_CC≤ V_CC(max))
PARAMETER
TEST CONDITIONS
-70
MIN MAX
-85
MIN MAX
-120
MIN MAX
UNIT
t_RC
Read cycle time
t_AA
Address access time
t_ACE
Chip enable access time
t_OE
Output enable to output valid
t_CLZ
Chip enable to output in low Z
t_OLZ
Output enable to output in low Z
t_CHZ
Chip disable to output in high Z
t_OHZ
Output disable to output in high Z
t_OH
Output hold from address change
Output load A
Output load B
Output load A
70
85
120
70
85
120
70
85
120
35
45
60
5
5
5
ns
0
0
0
0
25
0
35
0
45
0
25
0
25
0
35
10
10
10
t_RC
Address
t_AA
t_OH
D_OUT
Previous Data Valid
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = V_IL.
Figure 5. Read Cycle No. 1 (Address Access) ⁽¹⁾⁽²⁾
Data Valid
t_RC
CE
D_OUT
t_CLZ
t_ACE
High−Z
(1) WE is held high for a read cycle.
(2) Device is continuously selected: CE = OE = V_IL.
(3) Address is valid prior to or coincident with CE transition low.
Figure 6. Read Cycle No. 2 (CE Access) ^(1)(2)(3)
t_CHZ
High−Z
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