BQ4013_14 Datasheet, PDF (3/15 Pages) Texas Instruments – 128 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

Not Recommended For New Designs
bq4013/Y/LY
www.ti.com
SLUS121A – MAY 1999 – REVISED MAY 2007
When V_CC falls below the V_PFD threshold, the SRAM automatically write-protects the data. All outputs become
high impedance, and all inputs are treated as don't care. If a valid access is in process at the time of power-fail
detection, the memory cycle continues to completion. If the memory cycle fails to terminate within time t_WPT,
write-protection takes place.
As V_CC falls past V_PFD and approaches V_SO, the control circuitry switches to the internal lithium backup supply,
which provides data retention until valid V_CC is applied.
When V_CC returns to a level above the internal backup cell voltage, the supply is switched back to V_CC. After V_CC
ramps above the V_PFD threshold, write-protection continues for a time t_CER (120 ms maximum in 5-V system, 85
ms maximum in 3.3-V system) to allow for processor stabilization. Normal memory operation may resume after
this time.
The internal coin cells used by the bq4013/Y/LY have an extremely long shelf life and provide data retention for
more than 10 years in the absence of system power.
As shipped from TI, the integral lithium cells of the MT-type module are electrically isolated from the memory.
(Self-discharge in this condition is approximately 0.5% per year.) Following the first application of V_CC, this
isolation is broken, and the lithium backup provides data retention on subsequent power-downs.
BLOCK DIAGRAM
DIP MODULE
bq4013/Y/LY
MA PACKAGE
OE
A₀ - A₁₆
128 k × 8
SRAM
WE
Block
DQ₀ - DQ₇
Power
CE_CON
CE
Power-Fail
V_CC
Control
MODE
Not selected
Output disable
Read
Write
Lithium
Cell
+
UDG-06075
TRUTH TABLE
CE
WE
OE
H
X
X
L
H
H
L
H
L
L
L
X
I/O OPERATION
High-Z
High-Z
D_OUT
D_IN
POWER
Standby
Active
Active
Active
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