BQ4013_14 Datasheet, PDF (2/15 Pages) Texas Instruments – 128 k ´ 8 NONVOLATILE SRAM (5 V, 3.3 V)

bq4013/Y/LY
Not Recommended For New Designs
SLUS121A – MAY 1999 – REVISED MAY 2007
NAME
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
A₁₁
A₁₂
A₁₃
A₁₄
A₁₅
A₁₆
CE
DQ₀
DQ₁
DQ₂
DQ₃
DQ₄
DQ₅
DQ₆
DQ₇
NC
OE
V_CC
V_SS
WE
TERMINAL
NUMBER
12
11
10
9
8
7
6
5
27
26
23
25
4
28
3
31
2
22
13
14
15
17
18
19
20
21
1
30
24
32
16
29
DEVICE INFORMATION
Table 1. TERMINAL FUNCTIONS
I/O
DESCRIPTION
I
I
I
I
I
I
I
I
I
Address inputs
I
I
I
I
I
I
I
I
I
Chip-enable input
I/O
I/O
I/O
I/O
Data input/output
I/O
I/O
I/O
I/O
-
No connect
-
I
Output enable input
I
Supply voltage input
-
Ground
I
Write enable input
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FUNCTIONAL DESCRIPTION
When power is valid, the bq4013/Y/LY operates as a standard CMOS SRAM. During power-down and power-up
cycles, the bq4013/Y/LY acts as a nonvolatile memory, automatically protecting and preserving the memory
contents.
Power-down/power-up control circuitry constantly monitors the V_CC supply for a power-fail-detect threshold V_PFD.
The bq4013 monitors for V_PFD = 4.62 V typical for use in 5-V systems with 5% supply tolerance. The bq4013Y
monitors for V_PFD = 4.37 V typical for use in 5-V systems with 10% supply tolerance. The bq4013LY monitors for
V_PFD = 2.90 V (typ) for use in 3.3-V systems.
2
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