LM3S5B91 Datasheet, PDF (850/1331 Pages) Texas Instruments – Stellaris® LM3S5B91 Microcontroller

Inter-Integrated Circuit Sound (I²S) Interface
Register 13: I²S Module Configuration (I2SCFG), offset 0xC00
This register enables the transmit and receive serial engines and sets the source of the I2S0TXMCLK
and I2S0RXMCLK signals.
I2S Module Configuration (I2SCFG)
Base 0x4005.4000
Offset 0xC00
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RXSLV TXSLV
reserved
RXEN TXEN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
R/W
R/W
RO
RO
R/W
R/W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
RXSLV
Type
RO
R/W
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
Use External I2S0RXMCLK
Value Description
0 The receiver uses the internally generated MCLK as the
I2S0RXMCLK signal. See “Clock Control” on page 827 for
information on how to program the I2S0RXMCLK.
1 The receiver uses the externally driven I2S0RXMCLK signal.
4
TXSLV
R/W
0
Use External I2S0TXMCLK
Value Description
0 The transmitter uses the internally generated MCLK as the
I2S0TXMCLK signal. See “Clock Control” on page 827 for
information on how to program the I2S0TXMCLK.
1 The transmitter uses the externally driven I2S0TXMCLK signal.
3:2
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
1
RXEN
R/W
0
Serial Receive Engine Enable
Value Description
0 Disables the serial receive engine.
1 Enables the serial receive engine.
850
January 20, 2012
Texas Instruments-Production Data