LM3S5B91 Datasheet, PDF (1005/1331 Pages) Texas Instruments – Stellaris® LM3S5B91 Microcontroller

Stellaris^® LM3S5B91 Microcontroller
OTG A / Host Mode
USB Receive Control and Status Endpoint 1 Low (USBRXCSRL1)
Base 0x4005.0000
Offset 0x116
Type R/W, reset 0x00
7
6
5
4
3
2
1
0
CLRDT STALLED REQPKT FLUSH ^{DATAERR /} ERROR
NAKTO
FULL
RXRDY
Type W1C
R/W
R/W
R/W
R/W
R/W
RO
R/W
Reset
0
0
0
0
0
0
0
0
Bit/Field
7
6
5
4
Name
CLRDT
STALLED
REQPKT
FLUSH
Type
W1C
R/W
R/W
R/W
Reset
0
0
0
0
Description
Clear Data Toggle
Writing a 1 to this bit clears the DT bit in the USBRXCSRHn register.
Endpoint Stalled
Value Description
0 A STALL handshake has not been received.
1 A STALL handshake has been received. The EPn bit in the
USBRXIS register is also set.
Software must clear this bit.
Request Packet
Value Description
0 No request.
1 Requests an IN transaction.
This bit is cleared when RXRDY is set.
Flush FIFO
Value Description
0 No effect.
1 Flushes the next packet to be read from the endpoint receive
FIFO. The FIFO pointer is reset and the RXRDY bit is cleared.
Note that if the FIFO is double-buffered, FLUSH may have to be set
twice to completely clear the FIFO.
Important: ^{This bit should only be set when the RXRDY bit is set. At}
other times, it may cause data to be corrupted.
January 20, 2012
Texas Instruments-Production Data
1005