TM4C1297NCZAD Datasheet, PDF (832/1750 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Table 11-9. EPI Host-Bus 16 Signal Connections (continued)
EPI Signal
CSCFG
BSEL
HB16 Signal (MODE
=ADMUX)
HB16 Signal (MODE
=ADNOMUX (Cont.
Read))
HB16 Signal
(MODE
=XFIFO)
0x0
X
ALE
ALE
-
0x1
X
CSn
CSn
CSn
0x2
X
CS0n
CS0n
CS0n
EPI0S30
0x3
X
ALE
ALE
-
0x4
X
ALE
ALE
-
0x5
X
CS0n
CS0n
-
0x6
X
EPI0S31
X
X
ALE
Clock^d
ALE
Clock^d
-
Clock^d
EPI0S32
X
X
iRDY
iRDY
iRDY
EPI0S33
X
X
CS3n
CS3n
X
EPI0S34
X
X
CS2n
CS2n
X
EPI0S35
X
X
CRE
CRE
X
a. "X" indicates the state of this field is a don't care.
b. In this mode, half-word accesses are used. A0 is the LSB of the address and is equivalent to the internal Cortex-M3 A1
address. This pin should be connected to A0 of 16-bit memories.
c. When an entry straddles several row, the signal configuration is the same for all rows.
d. The clock signal is not required for this mode.
The RDYEN in the EPIHBnCFG enables the monitoring of the external iRDY pin to stall accesses.
On the rising edge of EPI clock, if iRDY is low, access is stalled. The IRDYDLY can program the
number of EPI clock cycles in advance to the stall (1,2 or 3) as shown in Figure 11-5 on page 833.
This is a conceptual timing diagram of how the iRDY signal works with different IRDYDLY
configurations. When enabled, the iRDY stalls the EPI's internal states, while IRDYDLY controls the
delay pipeline when this stall takes affect. The iRDY signal can be connected to multiple devices
with a pull up resistor as shown in Figure 11-6 on page 833. Note that when multiple PSRAMs are
connected to iRDY, the EPIHPnCFG registers must be programmed to the same iRDY signal polarity
through the IRDYINV bit. When connected to a PSRAM, iRDY is used to control the address to
data latency.
832
June 18, 2014
Texas Instruments-Production Data