TM4C1297NCZAD Datasheet, PDF (1325/1750 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1297NCZAD Microcontroller
Register 9: I²C Master Configuration (I2CMCR), offset 0x020
This register configures the mode (Master or Slave), and sets the interface for test mode loopback.
I2C Master Configuration (I2CMCR)
I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0x020
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
SFE
MFE
reserved
LPBK
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RO
RO
RO
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
SFE
Type
RO
RW
Reset Description
0x0000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
I²C Slave Function Enable
Value Description
0 Slave mode is disabled.
1 Slave mode is enabled.
4
MFE
RW
0
I²C Master Function Enable
Value Description
0 Master mode is disabled.
1 Master mode is enabled.
3:1
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
LPBK
RW
0
I²C Loopback
Value Description
0 Normal operation.
1 The controller in a test mode loopback configuration.
June 18, 2014
Texas Instruments-Production Data
1325