TM4C1297NCZAD Datasheet, PDF (1463/1750 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1297NCZAD Microcontroller
Bit/Field
3
2
1
0
Name
BYTESWAP
reserved
BIGDEND
FMODE
Type
RW
RO
RW
RW
Reset
0
0
0
0
Description
This bit controls the bytelane ordering of the data on the output of the
DMA module. It works in conjunction with the big-endian bit. See the
big-endian description for configuration guidelines.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Big Endian Enable
Use this bit when the processor is operating in Big Endian mode and
writes to the frame buffers are less than 32-bits wide. Only in this
scenario do we need to change the byte alignment for data coming into
the FIFO from the frame buffer.
Value Description
0 Big Endian reordering disabled.
1 Big Endian reordering enabled.
The BIGEND and BYTESWAP bits control the byte lane ordering of the
data on the output of the DMA module.
Frame Mode
Value Description
0 One frame buffer (FB0 only) used
1 Two frame buffers used,. DMA ping-pongs between FB0 and
FB1 in this mode
June 18, 2014
Texas Instruments-Production Data
1463