TM4C1297NCZAD Datasheet, PDF (297/1750 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1297NCZAD Microcontroller
Register 25: LDO Sleep Power Control (LDOSPCTL), offset 0x1B4
This register specifies the LDO output voltage in Sleep mode. This register should be configured
while in Run Mode. If the VADJEN bit is set, writes can be made to the VLDO field within the provided
encodings. The following table shows the maximum clock frequencies with respect to LDO Voltage.
Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage
Operating Voltage (LDO)
1.2
0.9
Maximum System Clock Frequency
120 MHz
30 MHz
PIOSC
16 MHz
16 MHz
LDO Sleep Power Control (LDOSPCTL)
Base 0x400F.E000
Offset 0x1B4
Type RW, reset 0x0000.0018
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
VADJEN
reserved
Type RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
VLDO
Type RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
Bit/Field
31
Name
VADJEN
Type
RW
Reset
0
Description
Voltage Adjust Enable
This bit enables the value of the VLDO field to be used to specify the
output voltage of the LDO in Sleep mode.
Value Description
0 The LDO output voltage is set to the factory default value in
Sleep mode. The value of the VLDO field does not affect the
LDO operation.
1 The LDO output value in Sleep mode is configured by the value
in the VLDO field.
30:8
reserved
RO
0x000.00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
297
Texas Instruments-Production Data