TM4C1297NCZAD Datasheet, PDF (561/1750 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1297NCZAD Microcontroller
Register 8: Hibernation Interrupt Clear (HIBIC), offset 0x020
This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources.
Writing a 1 to a bit clears the corresponding interrupt in the HIBRIS register.
Note: Writes to the RSTWK, PADIOWK and WC bits of this register are immediate and the status
may be read from the HIBRIS and HIBMIS registers without monitoring the WRC bit of the
HIBCTL register.
Note: All I/O wake sources are cleared by a write to either or both the RSTWK and PADIOWK bits.
This clears the source of interrupts for RSTWK, PADIOWK and the GPIOWAKESTAT register.
Hibernation Interrupt Clear (HIBIC)
Base 0x400F.C000
Offset 0x020
Type RW1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
VDDFAIL RSTWK PADIOWK WC
EXTW LOWBAT reserved RTCALT0
Type RO
RO
RO
RO
RO
RO
RO
RO
RW1C RW1C RW1C RW1C RW1C RW1C
RO
RW1C
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:8
7
6
5
4
3
Name
reserved
VDDFAIL
RSTWK
PADIOWK
WC
EXTW
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW1C
0
VDD Fail Interrupt Clear
Writing a 1 to this bit clears the VDDFAIL bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
Reset Pad I/O Wake-Up Interrupt Clear
Writing a 1 to this bit clears the RSTWK bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
Pad I/O Wake-Up Interrupt Clear
Writing a 1 to this bit clears the PADIOWK bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
Write Complete/Capable Interrupt Clear
Writing a 1 to this bit clears the WC bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
RW1C
0
External Wake-Up Interrupt Clear
Writing a 1 to this bit clears the EXTW bit in the HIBRIS and HIBMIS
registers.
Reads return the raw interrupt status.
June 18, 2014
561
Texas Instruments-Production Data