LM3S5749 Datasheet, PDF (830/947 Pages) Texas Instruments – Stellaris® LM3S5749 Microcontroller

Pulse Width Modulator (PWM)
Register 55: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset
0x06C
Register 56: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset
0x0AC
Register 57: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset
0x0EC
Register 58: PWM3 Dead-Band Rising-Edge Delay (PWM3DBRISE), offset
0x12C
The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A
signal when generating the PWM0 signal. If the dead-band generator is disabled through the
PWMnDBCTL register, the PWM0DBRISE register is ignored. If the value of this register is larger
than the width of a High pulse on the input PWM signal, the rising-edge delay consumes the entire
High time of the signal, resulting in no High time on the output. Care must be taken to ensure that
the input High time always exceeds the rising-edge delay. In a similar manner, PWM2 is generated
from PWM1A with its rising edge delayed; PWM4 is produced from PWM2A with its rising edge delayed;
and PWM6 is produced from PWM3A with its rising edge delayed.
If the Dead-Band Rising-Edge Delay mode is immediate (based on the DBRiseUpd field encoding
in the PWMnCTL register), this 16-bit DBRiseUpd value is used the next time the counter reaches
zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 795). If this register is rewritten before the actual update occurs, the previous value is
never used and is lost.
PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE)
Base 0x4002.8000
Offset 0x06C
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
Type RO
Reset
0
14
13
reserved
RO
RO
0
0
12
11
10
9
8
7
6
5
4
3
2
1
0
RiseDelay
RO
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:12
11:0
Name
reserved
RiseDelay
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Rise Delay
The number of clock ticks to delay the rising edge.
830
November 17, 2011
Texas Instruments-Production Data