LM3S5749 Datasheet, PDF (679/947 Pages) Texas Instruments – Stellaris® LM3S5749 Microcontroller

Stellaris® LM3S5749 Microcontroller
endpoint pair could be an interrupt endpoint. The address and size of the FIFOs attached to each
endpoint can be modified to fit the application's needs.
17.3.1.2
IN Transactions as a Device
When operating as a USB Device, data for IN transactions is handled through the FIFOs attached
to the transmit endpoints. The sizes of the FIFOs for the three configurable IN endpoints are
determined by the USB Transmit FIFO Start Address (USBTXFIFOADD) register. The maximum
size of a data packet that may be placed in a transmit endpoint’s FIFO for transmission is
programmable and is determined by the value written to the USB Maximum Transmit Data Endpoint
n (USBTXMAXPn) register for that endpoint. The endpoint’s FIFO can also be configured to use
double-packet or single-packet buffering. When double-packet buffering is enabled, two data packets
can be buffered in the FIFO, which also requires that the FIFO is at least two packets in size. When
double-packet buffering is disabled, only one packet can be buffered, even if the packet size is less
than half the FIFO size.
Note: The maximum packet size set for any endpoint must not exceed the FIFO size. The
USBTXMAXPn register should not be written to while data is in the FIFO as unexpected
results may occur.
Single-Packet Buffering
If the size of the transmit endpoint's FIFO is less than twice the maximum packet size for this endpoint
(as set in the USB Transmit Dynamic FIFO Sizing (USBTXFIFOSZ) register), only one packet
can be buffered in the FIFO and single-packet buffering is required. When each packet is completely
loaded into the transmit FIFO, the TXRDY bit in the USB Transmit Control and Status Endpoint
n Low (USBTXCSRLn) register must be set. If the AUTOSET bit in the USB Transmit Control and
Status Endpoint n High (USBTXCSRHn) register is set, the TXRDY bit is automatically set when
a maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, the
TXRDY bit must be set manually. When the TXRDY bit is set, either manually or automatically, the
packet is ready to be sent. When the packet has been successfully sent, both TXRDY and FIFONE
are cleared, and the appropriate transmit endpoint interrupt signaled. At this point, the next packet
can be loaded into the FIFO.
Double-Packet Buffering
If the size of the transmit endpoint's FIFO is at least twice the maximum packet size for this endpoint,
two packets can be buffered in the FIFO and double-packet buffering is allowed. As each packet is
loaded into the transmit FIFO, the TXRDY bit in the USBTXCSRLn register must be set. If the
AUTOSET bit in the USBTXCSRHn register is set, the TXRDY bit is automatically set when a
maximum-sized packet is loaded into the FIFO. For packet sizes less than the maximum, TXRDY
must be set manually. When the TXRDY bit is set, either manually or automatically, the packet is
ready to be sent. After the first packet is loaded, TXRDY is immediately cleared and an interrupt is
generated. A second packet can now be loaded into the transmit FIFO and TXRDY set again (either
manually or automatically if the packet is the maximum size). At this point, both packets are ready
to be sent. After each packet has been successfully sent, TXRDY is automatically cleared and the
appropriate transmit endpoint interrupt signaled to indicate that another packet can now be loaded
into the transmit FIFO. The state of the FIFONE bit in the USBTXCSRLn register at this point
indicates how many packets may be loaded. If the FIFONE bit is set, then another packet is in the
FIFO and only one more packet can be loaded. If the FIFONE bit is clear, then no packets are in
the FIFO and two more packets can be loaded.
Note: Double-packet buffering is disabled if an endpoint’s corresponding EPn bit is set in the USB
Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS) register. This bit is set
by default, so it must be cleared to enable double-packet buffering.
November 17, 2011
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