LM3S5749 Datasheet, PDF (364/947 Pages) Texas Instruments – Stellaris® LM3S5749 Microcontroller

General-Purpose Input/Outputs (GPIOs)
functions are enabled by setting the appropriate bit in the GPIO Alternate Function Select
(GPIOAFSEL) and GPIODEN registers and configuring the PMCx bit field in the GPIO Port Control
(GPIOPCTL) register to the numeric enoding shown in the table below. Note that each pin must be
programmed individually; no type of grouping is implied by the columns in the table.
Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0,
GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the
four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting
RST puts the pins back to their default state.
Table 9-1. GPIO Pins With Non-Zero Reset Values
GPIO Pins
PA[1:0]
PA[5:2]
PB[3:2]
PC[3:0]
Default State
UART0
SSI0
I²C0
JTAG/SWD
GPIOAFSEL GPIODEN GPIOPDR GPIOPUR
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
GPIOPCTL
0x1
0x1
0x1
0x3
Table 9-2. GPIO Pins and Alternate Functions (100LQFP)
IO
Pin Number
Multiplexed Function
PA0
26
U0Rx
PA1
27
U0Tx
PA2
28
SSI0Clk
PA3
29
SSI0Fss
PA4
30
SSI0Rx
PA5
31
SSI0Tx
PA6
34
I2C1SCL
PA7
35
I2C1SDA
PB0
66
CCP0
PB1
67
CCP1
PB2
72
I2C0SCL
PB3
65
I2C0SDA
PB4
92
C0-
PB5
91
C1-
PB6
90
C0+
PB7
89
NMI
PC0
80
TCK
PC1
79
TMS
PC2
78
TDI
PC3
77
TDO
PC4
25
CCP2
PC5
24
C1+
PC6
23
CCP3
PC7
22
CCP4
PD0
10
CAN0Rx
Multiplexed Function
SWCLK
SWDIO
SWO
364
November 17, 2011
Texas Instruments-Production Data