AMC7812B_14 Datasheet, PDF (80/93 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
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Power-Down Register (Read or Write, Address = 6Bh, Default = 0000h)
After power-on or reset, all bits in the Power-Down Register are cleared to '0', and all the components controlled
by this register are either powered-down or off. The Power-Down Register allows the host to manage the
AMC7812B power dissipation. When not required, the ADC, the reference buffer amplifier, and any of the DACs
can be put into an inactive low-power mode to reduce current drain from the supply. The bits in the Power-Down
Register control this power-down function. Set the respective bit to '1' to activate the corresponding function.
MSB
BIT 15
0
BIT 14
PADC
BIT 13 BIT 12 BIT 11
PREF
PDAC
0
PDAC
1
BIT 10
PDAC
2
BIT 9
PDAC
3
BIT 8
PDAC
4
BIT 7
PDAC
5
BIT 6
PDAC
6
BIT 5 BIT 4 BIT 3 BIT 2
PDAC PDAC PDAC PDAC
7
8
9
10
BIT 1
PDAC
11
LSB
BIT 0
0
Bit 14
Bit 13
Bits[12:1]
PADC
Power-down mode control bit.
0 = The ADC is inactive in low-power mode.
1 = The ADC is in normal operating mode.
PREF
Internal reference in power-down mode control bit.
0 = The reference buffer amplifier is inactive in low-power mode.
1 = The reference buffer amplifier is powered on.
PDACn
DACn power-down control bit.
0 = DACn is inactive in low-power mode and its output buffer amplifier is in a Hi-Z state. The output pin of DACn is
internally switched from the buffer output to the analog ground through an internal resistor.
1 = DACn is in normal operating mode.
Device ID Register (Read-Only, Address = 6Ch, Default = 1221h)
Model and revision information.
Software Reset Register (Read or Write, Address = 7Ch, Default = NA)
The software reset register resets all registers to the default values, except for the DAC data register, DAC latch,
and DAC clear register. The software reset is similar to a hardware reset, which resets all registers including the
DAC data register, DAC latch, and DAC clear register. After a software reset, make sure that the DAC data
register, DAC latch, and DAC clear register are set to the desired values before the DAC is powered on.
SPI Mode
In SPI Mode, writing 6600h to this register forces the device reset.
I²C Mode
Writing to this register (with any data) forces the device to perform a software reset. Reading this register returns
an undefined value that must be ignored. Note that this register is 8-bit, instead of 16-bit. Both reading from and
writing to this register are single-byte operations. Writing data to the software reset register in I²C mode is
described in the following steps:
1. The master device asserts a start condition.
2. The master then sends the 7-bit AMC7812B slave address followed by a '0' for the direction bit, indicating a
write operation.
3. The AMC7812B asserts an acknowledge signal on SDA.
4. The master sends register address 7Ch.
5. The AMC7812B asserts an acknowledge signal on SDA.
6. The master sends a data byte.
7. The AMC7812B asserts an acknowledge signal on SDA.
8. The master asserts a stop condition to end the transaction.
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