AMC7812B_14 Datasheet, PDF (33/93 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
www.ti.com
SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
ADC Data Format
For a single-ended input, the conversion result is stored in straight binary format. For a differential input, the
results are stored in twos complement format.
SCLK Clock Noise Reduction
To avoid noise caused by the bus clock, TI recommends that no bus clock activity occur for at least the
conversion process time immediately after the ADC conversion starts.
Programmable Conversion Rate
The maximum conversion rate is 500 kSPS for a single channel in auto mode, as shown in Table 1. The
conversion rate is programmable through the CONV-RATE-[1:0] bits of the AMC configuration register 1. When
more than one channel is selected, the conversion rate is divided by the number of channels selected in ADC
channel register 0 and ADC channel register 1. In auto mode, the CONV-RATE-[1:0] bits determine the actual
conversion rate. In direct mode, the CONV-RATE-[1:0] bits limit the maximum possible conversion rate. The
actual conversion rate in direct mode is determined by the rate of the conversion trigger. Note that when a trigger
is issued, there may be a delay of up to 4 µs to internally synchronize and initiate the start of the sequential
channel conversion process. In both direct and auto modes, when the CONV-RATE-[1:0] bits are set to a value
other than the maximum rate ('00'), nap mode is activated between conversions. By activating nap mode, the
AI_DD supply current is reduced; see Figure 67.
CONV-RATE-1
0
0
1
1
CONV-RATE-0
0
1
0
1
Table 1. ADC Conversion Rate
t_ACQ
(µs)
0.375
2.375
6.375
14.375
t_CONV
(µs)
1.625
1.625
1.625
1.625
NAP
ENABLED
No
Yes
Yes
Yes
THROUGHPUT
(Single-Channel Auto Mode)
500 kSPS (default)
250 kSPS
125 kSPS
62.5 kSPS
Handshaking with the Host (see AMC configuration register 0)
The DAV pin and the DAVF (data available flag) bit in AMC configuration register 0 provide handshaking with the
host. Pin and bit status depend on the conversion mode (direct or auto); see Figure 84 and Figure 85. In direct
mode, after ADC-n-data registers of all selected channels are updated, the DAVF bit in AMC configuration
register 0 is set immediately to '1', and the DAV pin is active (low) to signify that new data are available. By
reading the ADC-n-data register or restarting via the external CNVT pin, the ADC clears the DAVF bit to '0' and
deactivates the DAV pin (high). If an internal convert start (ICONV bit) is used to start the new ADC conversion,
an ADC-n-data register must be read after the current conversion completes before a new conversion can be
started in order to reset the DAV status.
In auto-mode, after the ADC-n-data registers of the selected channels are updated, a pulse of 1 µs (low) appears
on the DAV pin to signify that new data are available. However, the DAVF bit is always cleared to '0' in auto-
mode.
Copyright © 2013, Texas Instruments Incorporated
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