AMC7812B_14 Datasheet, PDF (41/93 Pages) Texas Instruments – 12-Bit Analog Monitoring and Control Solution with Multichannel ADC, DACs, and Temperature Sensors

AMC7812B
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SBAS625A – SEPTEMBER 2013 – REVISED SEPTEMBER 2013
DAC Output
The output range is programmable from 0 V to (2 × V_REF) or from 0 V to (5 × V_REF), depending on the gain bits in
the DAC gain register. The maximum output is AV_CC. The output buffer amplifier is capable of generating rail-to-
rail voltages on its output, giving an output range of 0 V to AV_CC. The source and sink capabilities of the output
amplifier can be seen in the Typical Characteristics. The slew rate is 1.5 V/μs with a typical 1/4 to 3/4 scale
settling time of 3 μs with the output unloaded.
Double-Buffered DAC Data Registers
There are 12 double-buffered DAC data registers. Each DAC has an internal latch preceded by a DAC data
register. Data are initially written to an individual DAC-n-data register and then transferred to the corresponding
DAC-n latch. When the DAC-n latch is updated, the output of DAC-n changes to the newly set value. When the
host reads the register memory map location labeled DAC-n-data, the value held in the DAC-n latch is returned
(not the value held in the input DAC-n-data register).
Full-Scale Output Range
The full-scale output range of each DAC is set by the product of the value of the reference voltage times the gain
of the DAC output buffer (V_REF × gain). The gain bits of the DAC gain register set the output range of the
individual DAC-n. The full-scale output range of each DAC is limited by the analog power supply. The maximum
output from the DAC must not be greater than AV_CC, and the minimum output must not be less than AGND.
DAC Output After Power-On Reset
After power-on, the DAC output buffer is in power-down mode. The output buffer is in a Hi-Z state and the DACx-
OUT (where x = 0 to 11) output pin connects to the analog ground through an internal 10-kΩ resistor. After
power-on or a hardware reset, all DAC-n-data registers, DAC-n latches, and the DAC output are set to default
values (000h).
Load DAC Latch
See Figure 91 for the structure of the DAC register and DAC latch. The contents of the DAC-n latch determine
the output level of the DAC-n pin. After writing to the DAC-n-data register, the DAC latch can be loaded either in
asynchronous or synchronous mode.
In asynchronous mode (SLDAC-n bit = '0'), data are loaded into the DAC-n latch immediately after the write
operation. In synchronous mode (SLDAC-n bit = '1'), the DAC latch updates when the synchronous DAC loading
signal occurs. Setting the ILDAC bit in AMC configuration register 0 generates the loading signal.
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