TLK2201A_16 Datasheet, PDF (8/20 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

TLK2201A
TLK2201AI
SLLS572B – JUNE 2003 – REVISED SEPTEMBER 2007
Max Receive
Path Latency
31 Bit
Times
30 Bit
Times (Max)
INPUT DATA
K28.5 DXX.X DXX.X
K28.5 DXX.X DXX.X DXX.X K28.5
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RBC0
RBC1
RD(0−9)
Worst Case
Misaligned K28.5
Corrupt Data
DXX.X DXX.X K28.5 DXX.X DXX.X
Misalignment Corrected
K28.5 DXX.X DXX.X DXX.X K28.5
SYNC
Figure 5. Word Realignment Timing Characteristics Waveforms
Systems that do not require framed data may disable byte alignment by tying SYNCEN low.
When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.
The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the
SYNC pulse is present for the entire RBC0 period.
DATA RECEPTION LATENCY
The serial to parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 21 bit times and the
maximum latency is 31 bit times. The minimum latency in DDR mode is 27 bit times and maximum latency is 34
bit times.
RXP, RXN
10 Bit Code
t_{d(Rx latency)}
RD(0−9)
10 Bit Code
RBC0
Figure 6. Receiver Latency – TBI Normal Mode Shown
LOSS OF SIGNAL DETECTION
These devices have a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer
has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of
gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of
signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV.
The LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.
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