TLK2201A_16 Datasheet, PDF (13/20 Pages) Texas Instruments – ETHERNET TRANSCEIVERS

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TLK2201A
TLK2201AI
SLLS572B – JUNE 2003 – REVISED SEPTEMBER 2007
LVTTL OUTPUT SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
t_r(RBC)
t_f(RBC)
t_r
t_f
t_su(D1)
t_h(D1)
t_su(D2)
t_h(D2)
t_su(D3)
t_h(D3)
PARAMETER
Clock rise time
Clock fall time
Data rise timer
Data fall time
Data setup time (RD0..RD9),
Data valid prior to RBC0 rising)
Data hold time (RD0..RD9),
Data valid after RBC0 rising
Data setup time (RD0..RD4)
Data hold time (RD0..RD4)
Data setup time (RD0..RD9)
Data hold time (RD0..RD9)
TEST CONDITIONS
MIN TYP MAX UNIT
80% to 20% output voltage, C = 5 pF (see Figure 9) 0.3
0.3
1.5
ns
1.5
0.3
1.5
ns
0.3
1.5
TBI normal mode (see Figure 3)
2.5
ns
TBI normal mode (see Figure 3)
2
ns
DDR mode, R_ω = 125 MHz (see Figure 4)
2
ns
DDR mode, R_ω = 125 MHz (see Figure 4)
0.8
ns
TBI half-rate mode, R_ω = 125 MHz (see Figure 2)
2.5
ns
TBI half-rate mode, R_ω = 125 MHz (see Figure 2)
1.5
ns
TRANSMITTER TIMING REQUIREMENTS
over recommended operating conditions (unless otherwise noted)
t_su(D4)
t_h(D4)
t_su(D5)
t_h(D5)
t_r, t_f
PARAMETER
Data setup time (TD0..TD9)
Data hold time (TD0..TD9)
Data setup time (TD0..TD9)
Data hold time (TD0..TD9)
TD[0,9] Data rise and fall time
TBI modes
TEST CONDITIONS
DDR modes
See Figure 9
MIN TYP
1.6
0.8
0.7
0.5
MAX
2
UNIT
ns
ns
ns
Copyright © 2003–2007, Texas Instruments Incorporated
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