THS0842_14 Datasheet, PDF (8/31 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
electrical characteristics over recommended operating conditions with f_CLK = 80 MSPS and use
of internal voltage references, AV_DD = DV_DD = DRV_DD = 3 V, T_A = T_MIN to T_MAX, dual output bus mode
(unless otherwise noted) (continued)
dynamic performance^†
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Effective number of bits, ENOB
Signal-to-total harmonic distortion + noise, S/(THD+N)
Total harmonic distortion (THD)
Spurious free dynamic range (SFDR)
Analog input full-power bandwidth, BW
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
fin = 1 MHz
fin = 15 MHz
fin = 20 MHz
See Note 6
6.6 6.9
6.4 6.8
6.4 6.8
41.5 43.5
40 42.5
40 42.5
–51
–48.5
–48.5
48
53
47 52.2
46
52
600
Bits
dB
–46
–44 dB
–44
dB
MHz
Intermodulation distortion
f1 = 1 MHz, f2 = 1.02 MHz
50
dBc
I/Q channel crosstalk
AVDD = DVDD = DRVDD = 3.3 V
–52
dBc
† _{Based on analog input voltage of – 1 dBFS referenced to a 1.3 Vpp full-scale input range.}
NOTE 6: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which
an extra 3 dB attenuation is observed in the reconstructed output signal.
timing requirements
fclk
td(O)
th(O)
PARAMETER
Maximum clock rate (see Note 7)
Minimum clock rate
Output delay time (see timing diagram)
Output hold time from COUT or COUT to data invalid
td(pipe) Pipeline delay (latency)
td(a)
Aperture delay time
tj(a)
Aperture jitter
tdis
Disable time, OE rising to Hi-Z
ten
Enable time, OE falling to valid data
tsu(O) Output setup time from data to COUT or COUT
NOTE 7: Conversion rate is 1/2 the clock rate, fclk.
TEST CONDITIONS
CL = 10 pF
I data
Q data
MIN TYP MAX UNIT
80 MHz
10
kHz
9 ns
2
ns
5.5 5.5 5.5 _CLK
6.5 6.5 6.5 ^cycles
3
ns
1.5
ps, rms
5
ns
5
ns
8
7
ns
8
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