THS0842_14 Datasheet, PDF (4/31 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
Terminal Functions
TERMINAL
I/O
NAME
NO.
DESCRIPTION
AVDD
AVSS
27, 37, 41 I Analog supply voltage
28, 36, 40, I Analog ground
46
BG
29
O Band gap reference voltage. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected
between this terminal and AVSS for external filtering.
CLK
47
I Clock input. The input is sampled on each rising edge of CLK.
CML
COUT
COUT
DB7 – DB0
32
26
25
4 – 11
O Common mode level. This voltage is equal to (AVDD – AVSS)/2. An external 1-µF capacitor with a 0.1-µF
capacitor in parallel should be connected between this terminal and AVSS.
O Latch clock for the data outputs
O Inverted latch clock for the data outputs
O Data outputs. D7 is the MSB. This is the second bus. Data is output from the Q channel when dual bus
output mode is selected. Pin SELB selects the output mode.
DRVDD
DRVSS
DA7 – DA0
1, 13
12, 24
16 – 23
I Supply voltage for output drivers
I Ground for digital output drivers
I Data outputs for bus A. D7 is MSB. This is the primary bus. Data from both input channels can be output
on this bus or data from the I channel only. Pin SELB selects the output mode.
DVDD
DVSS
I–
45
I Digital supply voltage
43
I Digital ground
39
I Negative input for analog channel 0.
I+
38
I Positive input for analog channel 0.
NC
2,3,14,15
No connect. Reserved for future use
OE
48
I Output enable. A high on this terminal will disable the output bus.
PWDN_REF
33
I Power down for internal reference voltages. A high on this terminal will disable the internal reference
circuit.
Q–
35
I Negative input for analog channel 1
Q+
34
I Positive input for analog channel 1
REFB
30
I/O Reference voltage bottom. The voltage at this terminal defines the bottom reference voltage for the ADC.
Sufficient filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should
be connected between REFB and AVSS. Additionally, a 0.1-µF capacitor can be connected between REFT
and REFB.
REFT
31
I/O Reference voltage top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient
filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be
connected between REFT and AVSS. Additionally, a 0.1-µF capacitor can be connected between REFT
and REFB.
SELB
44
I Selects either single bus or data output or dual bus output data output. A low selects dual bus data output.
STBY
42
I Standby input. A high level on this terminal will power down the device.
4
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