THS0842_14 Datasheet, PDF (20/31 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
PRINCIPLES OF OPERATION
analog input (continued)
Positive
Analog
Input
I/Q+
1.5 + 0.25 V
1.5 V
I/Q+
1.5 – 0.25 V
Negative
Analog
Input
I/Q–
1.5 – 0.25 V
1.5 V
I/Q–
1.5 + 0.25 V
+0.5 V
Differential
0V
Input
1.0 Vp–p
–0.5 V
Figure 19. Differential Input Waveform With AV_DD = 3 V
The analog input can be dc coupled (see Figure 21) as long as the inputs are within the analog input common
mode voltage range. For example (see Figure 21), V+ and V– are signals centered on GND with a peak-to-peak
voltage of 2 V, and the circuit in Figure 21 is used to interface it with the THS0842. Assume AV_DD of the converter
is 3 V. Two problems have to be solved. The first is to shift CML from 0 V to 1.5 V (AV_DD/2). To do that, a V_bias
voltage and an adequate ratio of R1 and R2 have to be selected. For instance, if V_bias = AV_DD = 3 V, then R1
= R2. The second is that the differential voltage has to be reduced from 4 V (2 x 2 V) to 1 V, and for that an
attenuation of 4 to1 is needed. The attenuation is determined by the relation: (R3||2R2)/((R3||2R2) + 2R1). One
possible solution is R1 = R2 = R3 = 150 Ω. In this case, moreover, the input impedance (2R1 + (R3||2R2)) will
be 400 Ω. The values can be changed to match any other input impedance. A capacitor, C, connected from I/Q
IN+ to I/Q IN– will help filter any high frequency noise on the inputs, also improving performance. Note, that the
chosen value of capacitor C must take into account the highest frequency component of the analog input signal.
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