THS0842_14 Datasheet, PDF (7/31 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
electrical characteristics over recommended operating conditions with f_CLK = 80 MSPS and use
of internal voltage references, AV_DD = DV_DD = DRV_DD = 3 V, T_A = T_MIN to T_MAX, dual output bus mode
(unless otherwise noted) (continued)
dc accuracy
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Integral nonlinearity (INL), best-fit
Differential nonlinearity (DNL)
Offset error
Gain error
See Note 1
See Note 2
TA = –40°C to 85°C, (see Note 3)
TA = –40°C to 85°C
TA = –40°C to 85°C
–2.2 ± 1.5
–1 ± 0.7
± 0.1
± 7.1
2.2 LSB
2 LSB
5 %FS
%FS
Offset match
TA = –40°C to 85°C, (see Note 4)
Gain match
TA = –40°C to 85°C, (see Note 5)
Missing codes – no missing codes assured
–1 ± 0.1
–5
1 LSB
1 LSB
NOTES:
1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero
occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.
The deviation is measured from the center of each particular code to the best fit line between these two endpoints.
2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.
3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).
Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).
4. Offset match is the change in offset error between I and Q channels.
5. Gain match is the change in gain error between I and Q channels.
analog input
PARAMETER
CI
Input capacitance
TEST CONDITIONS
MIN TYP MAX UNIT
4
pF
reference input (AV_DD = DV_DD = DRV_DD = 3.6 V)
PARAMETER
Rref Reference input resistance
Iref Reference input current
TEST CONDITIONS
MIN TYP MAX UNIT
200
Ω
5
mA
reference outputs
PARAMETER
V(REFT)
V(REFB)
Reference top voltage
Reference bottom voltage
VREFB–VREFB
TEST CONDITIONS
AVDD = 3 V
Absolute min/max values valid
and tested for AVDD = 3 V
MIN
TYP
2 + [(AVDD – 3)/2]
1 + [(AVDD – 3)/2]
0.9
1
MAX UNIT
V
1.3 V
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