THS0842_14 Datasheet, PDF (22/31 Pages) Texas Instruments – DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT
SLAS246A – DECEMBER 1999 – REVISED AUGUST 2000
PRINCIPLES OF OPERATION
ac coupled input (continued)
THS0842
VIN+
R1
AIN+
R2
VIN–
R1
Vbias
C
R3
100
pF
AIN–
R2
Vbias
CML
REFT
REFB
Figure 21. DC-Coupled Differential Input Circuit
For many applications, ac coupling offers a convenient way for biasing the analog input signal at the proper
signal range. Figure 20 shows a typical configuration. To maintain the outlined specifications, the component
values need to be carefully selected. The most important issue is the positioning of the 3 dB high-pass corner
point f_{– 3 dB}, which is a function of R (R_S + R_SW as shown in Figure 18) and the parallel combination of C₁ and
+ ǒ Ǔ C2, called Ceq. This is given by the following equation:
f–3 _dB 1 ÷ 2π x R x Ceq
Since C1 is typically a large electrolytic or tantalum capacitor, the impedance becomes inductive at higher
frequencies. Adding a small ceramic or polystyrene capacitor, C2 of approximately 0.01 µF, which is not
inductive within the frequency range of interest, maintains low impedance.
analog input, single-ended connection
The configuration shown in Figure 23 may be used with a single-ended ac coupled input. If I/Q is a 1 V_pp
sinewave, then I/Q IN+ is a 1 V_pp sinewave riding on a positive voltage equal to CML (see Figure 22). The
converter will be at positive full scale when I/Q IN+ is at CML+0.5V (I/Q IN+ – I/Q IN– = 0.5 V) and will be at
negative full scale when I/Q IN+ is equal to CML – 0.5 V (I/Q IN+ – I/Q IN– = –0.5 V). Sufficient headroom must
be provided such that the input voltage never goes above 3.3 V or below AGND. The simplest way is to use
the dc bias source output (CML) of the THS0842.
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