DS92LV1023E_14 Datasheet, PDF (8/21 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Serializer

DS92LV1023E
SNLS187B – MARCH 2005 – REVISED APRIL 2013
www.ti.com
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Parameter
Test Conditions
Min
Typ
Max Units
t_LLHT
t_LHLT
Bus LVDS Low-to-High
Transition Time
Bus LVDS High-to-Low Transition Time
R_L = 27Ω
C_L=10pF to GND
Figure 3
(1)
0.2
0.4
ns
0.25
0.4
ns
t_DIS
t_DIH
t_HZD
t_LZD
t_ZHD
t_ZLD
t_SPW
t_PLD
t_SD
t_DJIT
DIN (0-9) Setup to TCLK
DIN (0-9) Hold from TCLK
DO ± HIGH to
TRI-STATE Delay
DO ± LOW to TRI-STATE Delay
DO ± TRI-STATE to HIGH Delay
DO ± TRI-STATE to LOW Delay
SYNC Pulse Width
Serializer PLL Lock Time
Serializer Delay
Deterministic Jitter
R_L = 27Ω,
C_L=10pF to GND
Figure 5
R_L = 27Ω,
C_L=10pF to GND
Figure 6
(2)
R_L = 27Ω
Figure 8
R_L = 27Ω, Figure 9
R_L = 27Ω,
C_L=10pF to GND,
(3)
30 MHz
66 MHz
0
ns
4.0
ns
3
10
ns
3
10
ns
5
10
ns
6.5
10
ns
5*t_TCP
ns
510*t_TCP
513*t_TCP
ns
t_TCP+ 1.0 t_TCP+ 2.0 t_TCP+ 3.0 ns
-350
-45
190
ps
-200
-70
80
ps
t_RJIT
Random Jitter
R_L = 27Ω,
C_L=10pF to GND
19
25
ps
(RMS)
(1) t_LLHT and t_LHLT specifications are Guranteed By Design (GBD) using statistical analysis.
(2) Because the Serializer is in TRI-STATE mode, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
(3) t_DJIT specifications are Guranteed By Design using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 2. “Worst Case” Serializer ICC Test Pattern
Figure 3. Serializer Bus LVDS Output Load and Transition Times
Figure 4. Serializer Input Clock Transition Time
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