DS92LV1023E_14 Datasheet, PDF (12/21 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Serializer

DS92LV1023E
SNLS187B – MARCH 2005 – REVISED APRIL 2013
APPLICATION INFORMATION
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USING THE SERIALIZER AND DESERIALIZER CHIPSET
The Serializer and Deserializer chipset is an easy to use transmitter and receiver pair that sends 10 bits of
parallel LVTTL data over a serial Bus LVDS link up to 660 Mbps. An on-board PLL serializes the input data and
embeds two clock bits within the data stream. The Deserializer uses a separate reference clock (REFCLK) and
an onboard PLL to extract the clock information from the incoming data stream and then deserialize the data.
The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output
high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. In addition, the
constant current source nature of the Bus LVDS outputs minimizes the slope of the speed vs. I_CC curve of
conventional CMOS designs.
TRANSMITTING DATA
Once you power up the Serializer and Deserializer, they must be phase locked to each other to transmit data.
Phase locking occurs when the Deserializer locks to incoming data or when the Serializer sends patterns. The
Serializer sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCK output of the
Deserializer remains high until it has locked to the incoming data stream. Connecting the LOCK output of the
Deserializer to one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to
achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCK output is low, data at the Deserializer outputs (ROUT0-9) is valid, except for the
specific case of loss of lock during transmission which is further discussed in the "Recovering from LOCK Loss"
section below.
HOT INSERTION
All the BLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 12.
PCB CONSIDERATIONS
The Bus LVDS Serializer and Deserializer should be placed as close to the edge connector as possible. In
multiple Deserializer applications, the distance from the Deserializer to the slot connector appears as a stub to
the Serializer driving the backplane traces. Longer stubs lower the impedance of the bus, increase the load on
the Serializer, and lower the threshold margin at the Deserializers. Deserializer devices should be placed much
less than one inch from slot connectors. Because transition times are very fast on the Serializer Bus LVDS
outputs, reducing stub lengths as much as possible is the best method to ensure signal integrity.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configuration of a backplane, through a PCB
trace, or through twisted pair cable. In point-to-point configuration, the transmission media need only be
terminated at the receiver end. Please note that in point-to-point configuration, the potential of offsetting the
ground levels of the Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1.2V
common mode range at the receiver inputs.
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