DS92LV1023E_14 Datasheet, PDF (5/21 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Serializer

DS92LV1023E
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SNLS187B – MARCH 2005 – REVISED APRIL 2013
TRI-STATE
The Serializer enters TRI-STATE when the DEN pin is driven low. This puts both driver output pins (DO+ and
DO−) into TRI-STATE. When you drive DEN high, the Serializer returns to the previous state, as long as all other
control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
When you drive the REN pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins
(ROUT0–ROUT9) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the
PLL.
DIN0 Held Low-DIN1 Held High Creates an RMT Pattern
DIN8 Held Low-DIN9 Held High Creates an RMT Pattern
DIN4 Held Low-DIN5 Held High Creates an RMT Pattern
Figure 1. RMT Patterns Seen on the Bus LVDS Serial Output
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