DS92LV1023E_14 Datasheet, PDF (11/21 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Serializer

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DS92LV1023E
SNLS187B – MARCH 2005 – REVISED APRIL 2013
SW - Setup and Hold Time (Internal Data Sampling Window)
t_DJIT - Serializer Output Bit Position Jitter that results from Jitter on TCLK
t_RNM = Receiver Noise Margin Time
Figure 10. Receiver Bus LVDS Input Skew Margin
V_OD = (DO⁺)–(DO^−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
Figure 11. V_OD Diagram
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