DS92LV1023E_14 Datasheet, PDF (3/21 Pages) Texas Instruments – 30-66 MHz 10 Bit Bus LVDS Serializer

DS92LV1023E
www.ti.com
SNLS187B – MARCH 2005 – REVISED APRIL 2013
Data Transfer
After initialization, the Serializer will accept data from inputs DIN0–DIN9. The Serializer uses the TCLK input to
latch incoming Data. The TCLK_R/F pin selects which edge the Serializer uses to strobe incoming data.
TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the SYNC
inputs is high for 5*TCLK cycles, the data at DIN0-DIN9 is ignored regardless of clock edge.
After determining which clock edge to use, a start and stop bit, appended internally, frame the data bits in the
register. The start bit is always high and the stop bit is always low. The start and stop bits function as the
embedded clock bits in the serial stream.
The Serializer transmits serialized data and clock bits (10+2 bits) from the serial data output (DO±) at 12 times
the TCLK frequency. For example, if TCLK is 66 MHz, the serial rate is 66 × 12 = 792 Mega-bits-per-second.
Since only 10 bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if
TCLK = 66 MHz, the payload data rate is 66 × 10 = 660 Mbps. The data source provides TCLK and must be in
the range of 30 MHz to 66 MHz nominal.
The Serializer outputs (DO±) can drive a point-to-point connection or in limited multi-point or multi-drop
backplanes. The outputs transmit data when the enable pin (DEN) is high, PWRDN = high, and SYNC1 and
SYNC2 are low. When DEN is driven low, the Serializer output pins will enter TRI-STATE.
When the Deserializer synchronizes to the Serializer, the LOCK pin is low. The Deserializer locks to the
embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low. Otherwise
ROUT0–ROUT9 is invalid.
The ROUT0-ROUT9 pins use the RCLK pin as the reference to data. The polarity of the RCLK edge is controlled
by the RCLK_R/F input.
ROUT(0-9), LOCK and RCLK outputs will drive a maximum of three CMOS input gates (15 pF load) with a 66
MHz clock.
Resynchronization
When the Deserializer PLL locks to the embedded clock edge, the Deserializer LOCK pin asserts a low. If the
Deserializer loses lock, the LOCK pin output will go high and the outputs (including RCLK) will enter TRI-STATE.
The user's system monitors the LOCK pin to detect a loss of synchronization. Upon detection, the system can
arrange to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. Multiple resynchronization approaches
are possible. One recommendation is to provide a feedback loop using the LOCK pin itself to control the sync
request of the Serializer (SYNC1 or SYNC2). Dual SYNC pins are provided for multiple control in a multi-drop
application. Sending sync patterns for resynchronization is desirable when lock times within a specific time are
critical. However, the Deserializer can lock to random data, which is discussed in the next section.
Random Lock Initialization and Resynchronization
The initialization and resynchronization methods described in their respective sections are the fastest ways to
establish the link between the Serializer and Deserializer. However, the DS92LV1224 can attain lock to a data
stream without requiring the Serializer to send special SYNC patterns. This allows the DS92LV1224 to operate in
“open-loop” applications. Equally important is the Deserializer's ability to support hot insertion into a running
backplane. In the open loop or hot insertion case, we assume the data stream is essentially random. Therefore,
because lock time varies due to data stream characteristics, we cannot possibly predict exact lock time. The
primary constraint on the “random” lock time is the initial phase relation between the incoming data and the
REFCLK when the Deserializer powers up. As described in the next paragraph, the data contained in the data
stream can also affect lock time.
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