DS90CP04_14 Datasheet, PDF (8/25 Pages) Texas Instruments – DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS90CP04
SNLS154I – JANUARY 2002 – REVISED APRIL 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. ⁽¹⁾
Symbol
Parameter
Conditions
Min
Typ ⁽²⁾
Max
Units
t_SKCC
t_JIT
Output Channel to Channel Skew Difference in propagation delay (t_PLHD
or t_PHLD) among all output channels
in Broadcast mode (any one input to
0
all outputs).
Jitter ⁽⁶⁾
Alternating 1 and 0 Pattern
750 MHz
50
100
ps
1.6
2.5
psrms
1.25 GHz
1.6
2.5
psrms
K28.5 Pattern
1.5 Gb/s
10
40
psp-p
2.5 Gb/s
PRBS 2²³-1 Pattern
27
60
psp-p
1.5 Gb/s
25
40
psp-p
2.5 Gb/s
40
70
psp-p
t_ON
LVDS Output Enable Time
Time from LOAD = LH or SELx to
OUT± change from TRI-STATE to
50
150
300
ns
active.
t_OFF
LVDS Output Disable Time
Time from LOAD = LH or SELx to
OUT± change from active to TRI-
STATE.
3
5
ns
t_SW
LVDS Switching Time
Time from LOAD = LH to new switch
configuration effective for OUT±.
50
150
ns
t_SEL
SELx to OUT±
Configuration select to new data at
OUT±.
SWITCHING CHARACTERISTICS — Serial control Interface (⁽⁸⁾)
50
150
ns
F_SCLK
T_DCCLK
SCLK Clock Frequency
CSCLK Duty Cycle
RSCLK Duty Cycle
0
Input SCLK Duty Cycle set at 50%
45
100
MHz
55
%
t_S
SI–SCLK or MODE–SCLK Setup From SI or MODE Input Data to
Time
SCLK Rising Edge
1.5
ns
t_H
SCLK–SI or SCLK–MODE Hold
Time
From SCLK Rising Edge to SI or
MODE Input Data
1
ns
t_DSO
SCLK to RSO or CSO Delay
From SCLK to RSO or CSO
1.5
4
ns
t_DSCLK
SCLK to RSCLK or CSCLK Delay From SCLK to RSCLK or CSCLK
4.0
8.5
ns
t_DSDIF
|SCLK to RSCLK or
CSCLK–SCLK to RSO or CSO|
Propagation Delay Difference
between t_DSO and t_DSCLK
1.5
4.5
ns
T_RISE
Logic Low to High Transition Time 20% to 80% at RSO, CSO, RSCLK,
or CSCLK
1.5
ns
T_FALL
Logic High to Low Transition Time 80% to 20% at RSO, CSO, RSCLK,
or CSCLK
1.5
ns
(8) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
8
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