DS90CP04_14 Datasheet, PDF (13/25 Pages) Texas Instruments – DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS90CP04
www.ti.com
SNLS154I – JANUARY 2002 – REVISED APRIL 2013
FUNCTIONAL DESCRIPTIONS
Programming with the Serial Interface
The configuration of the internal multiplexer is programmed through a simple serial interface consisting of serial
clock SCLK and serial input data line SI. The serial interface is designed for easy expansion to larger switch
array. A replicated output serial interface (RSCLK, RSO) is provided for propagating the control data to the
downstream device in the row of an array of DS90CP04 devices in a matrix. A similar replicated serial interface
(CSCLK, CSO) is provided for propagating the control data to the downstream devices in the first column of the
device matrix. Through this scheme, user can program all the devices in the matrix through one serial control bus
(SCLK and SI) with the use of the feed-through replicated control bus at RSCLK and RSO, CSCLK and CSO.
To program the configuration of the switch, a 30-bit control word is sent to the device. The first 6 bits shift the
start frame into SI. The only two valid start frames are 1F'h for a configuration load and 1E'h for a configuration
read. The start frame is followed by the row and column addresses of the device to be accessed, as well as the
switch configuration of the four channels of the device. Table 1 and Table 2 are the bit definitions of the control
word. D29 is the first bit that shifts into SI.
Bit
D29–D24
D23–D18
D17–D12
D11–D9
D8–D6
D5–D3
D2–D0
Table 1. 30-Bit Control Word
Bit Length
6
6
6
3
3
3
3
Descriptions
The start frame for control word synchronization (01 1111'b = LOAD).
Specify the row address of the device to be access. The serial interface can access up to 64 devices in the
row.
Specify the column address of the device to be access. The serial interface can access up to 64 devices in
the column.
Specify the switch configuration for Output 1. See Table 2.
Specify the switch configuration for Output 2. See Table 2.
Specify the switch configuration for Output 3. See Table 2.
Specify the switch configuration for Output 4. See Table 2.
Table 2. Switch Configuration Data
MSB
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
LSB
0
1
0
1
0
1
0
1
OUT1± Connects to
OUT2± Connects to
OUT3± Connects to
Output 1 Tri-Stated
Output 2 Tri-Stated
Output 3 Tri-Stated
IN1±
IN1±
IN1±
IN2±
IN2±
IN2±
IN3±
IN3±
IN3±
IN4±
IN4±
IN4±
Invalid.
Use of these invalid combinations may cause loss of synchronization.
OUT4± Connects to
Output 4 Tri-Stated
IN1±
IN2±
IN3±
IN4±
Row and Column Addressing
The upper left device in an array of NxN devices is assigned row address 0, and column address 0. The devices
to its right have column addresses of 1 to N, whereas devices below it have row addresses of 1 to N. The Serial
Control Interface (SCLK and SI) is connected to the first device with the row and column addresses of 0. The
Serial Control Interface shifts in a control word containing the row and column address of the device it wants to
access. When the control data propagates through each device, the control word's address is internally
decremented by one before it is sent to the next row or column device. When the control data is sent out the
column interface (CSO and CSCLK) the row address is decremented by one. Similarly, when the column
address data is shifted out the row interface (RSO and RSCLK) the column address is decremented by one. By
the time the control word reaches the device it has been intended to program, both the row and column
addresses have been decremented to 0.
Each device constantly checks for the receipt of a frame start (D29-24=01 1111'b or 01 1110'b). When it detects
the proper start frame string, and the row and column addresses it receives are both 0, the device responds by
storing the switch configuration data of the 30-bit control word into its load register.
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