DS90CP04_14 Datasheet, PDF (7/25 Pages) Texas Instruments – DS90CP04 1.5 Gbps 4x4 LVDS Crosspoint Switch

DS90CP04
www.ti.com
SNLS154I – JANUARY 2002 – REVISED APRIL 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless other specified. ⁽¹⁾
Symbol
Parameter
Conditions
Min
V_TH
Differential Input High Threshold V_CM = 0.05V or 1.2V or 2.45V, V_DD =
(3)
2.5V
V_TL
Differential Input Low Threshold
V_CM = 0.05V or 1.2V or 2.45V, V_DD =
2.5V
−50
V_ID
Differential Input Voltage
V_DD = 2.5V, V_CM = 0.05V to 2.45V
V_CMR
Common Mode Voltage Range
V_ID = 100 mV, V_DD = 2.5V
C_IN2
Input Capacitance
IN+ or IN− to V_SS
I_IN
Input Current
V_IN = 2.5V, V_DD = V_DDMAX or 0V
V_IN = 0V, V_DD = V_DDMAX or 0V
LVDS OUTPUT DC SPECIFICATIONS (OUT1±, OUT2±, OUT3±, OUT4±)
V_OD
ΔV_OD
Differential Output Voltage ⁽³⁾
Change in V_OD between
Complementary States
R_L = 100Ω between OUT+ and OUT−
(see Figure 4)
V_OS
Offset Voltage ⁽⁴⁾
ΔV_OS
Change in V_OS between
Complementary States
100
0.05
−10
−10
250
−35
1.125
−35
I_OZ
Output TRI-STATE Current
TRI-STATE Output
V_OUT = V_DD or V_SS
−10
I_OFF
Power Off Leakage Current
V_DD = 0V, V_OUT = 2.5V or GND
−10
I_OS
Output Short Circuit Current, One OUT+ or OUT− Short to GND
Complementary Output
OUT+ or OUT− Short to V_DD
I_OSB
Output Short Circuit Current, both OUT+ and OUT− Short to GND
Complementary Outputs
OUT+ and OUT− Short to V_CM
C_OUT2
Output Capacitance
OUT+ or OUT− to GND when TRI-
STATE
SUPPLY CURRENT
I_CCD
Total Supply Current
All inputs and outputs enabled,
terminated with differential load of
100Ω between OUT+ and OUT-.
I_CCZ
TRI-STATE Supply Current
TRI-STATE All Outputs
SWITCHING CHARACTERISTICS—LVDS OUTPUTS (⁽⁵⁾, ⁽⁶⁾, ⁽⁷⁾)
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at
Time
200 Mb/s, measure between 20%
100
t_HLT
Differential High to Low Transition ^{and 80% of VOD.}
Time
100
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V_OD
500
between input to output.
500
t_SKD1
Pulse Skew
|t_PLHD–t_PHLD|
Typ ⁽²⁾
0
0
3.5
400
1.25
−15
15
−15
15
5.5
220
10
135
135
750
750
0
Max
50
V_DD
3.25
+10
+10
475
35
1.375
35
+10
+10
-40
40
-30
30
300
20
160
160
1200
1200
30
Units
mV
mV
mV
V
pF
µA
µA
mV
mV
V
mV
µA
µA
mA
mA
mA
mA
pF
mA
mA
ps
ps
ps
ps
ps
(3) Differential output voltage V_OD is defined as |OUT+–OUT−|. Differential input voltage V_ID is defined as |IN+–IN−|.
(4) Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
(5) Differential output voltage V_OD is defined as |OUT+–OUT−|. Differential input voltage V_ID is defined as |IN+–IN−|.
(6) Characterized from any input to any one differential LVDS output running at the specified data rate and data pattern, with all other 3
channels running K28.5 pattern at 1.25 Gb/s asynchronously to the channel under test. Jitter is not production-tested, but ensured
through characterization on sample basis. Random Jitter is measured peak to peak with a histogram including 1000 histogram window
hits. K28.5 pattern is repeating bit streams of (0011111010 1100000101). This deterministic jitter or DJ pattern is measured to a
histogram mean with a sample size of 350 hits. Like RJ the Total Jitter or TJ is measured peak to peak with a histogram including 3500
window hits.
(7) The LVCMOS input and output AC specifications may also be verified and tested using an input attenuation network instead of a power
splitter.
Copyright © 2002–2013, Texas Instruments Incorporated
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